Test MP+dmb.sy+[fr-rf]-data-wsi-rfi-addr

AArch64 MP+dmb.sy+[fr-rf]-data-wsi-rfi-addr
"DMB.SYdWW Rfe FrLeave RfBack DpDatadW Wsi Rfi DpAddrdR Fre"
Cycle=Rfi DpAddrdR Fre DMB.SYdWW Rfe FrLeave RfBack DpDatadW Wsi
Relax=
Safe=Rfi Rfe Fre Wsi DMB.SYdWW DpAddrdR DpDatadW [FrLeave,RfBack]
Prefetch=0:x=F,0:y=W,1:y=F,1:x=T
Com=Rf Fr Rf
Orig=DMB.SYdWW Rfe FrLeave RfBack DpDatadW Wsi Rfi DpAddrdR Fre
{
0:X1=x; 0:X3=y;
1:X1=y; 1:X4=z; 1:X9=x;
2:X1=y;
}
 P0          | P1                  | P2          ;
 MOV W0,#1   | LDR W0,[X1]         | MOV W0,#2   ;
 STR W0,[X1] | LDR W2,[X1]         | STR W0,[X1] ;
 DMB SY      | EOR W3,W2,W2        |             ;
 MOV W2,#1   | ADD W3,W3,#1        |             ;
 STR W2,[X3] | STR W3,[X4]         |             ;
             | MOV W5,#2           |             ;
             | STR W5,[X4]         |             ;
             | LDR W6,[X4]         |             ;
             | EOR W7,W6,W6        |             ;
             | LDR W8,[X9,W7,SXTW] |             ;
Observed
    z=2; y=2; x=1; 1:X8=1; 1:X6=2; 1:X2=0; 1:X0=2;
and z=2; y=1; x=1; 1:X8=1; 1:X6=2; 1:X2=0; 1:X0=2;
and z=2; y=1; x=1; 1:X8=0; 1:X6=2; 1:X2=0; 1:X0=2;
and z=2; y=2; x=1; 1:X8=1; 1:X6=2; 1:X2=0; 1:X0=1;
and z=2; y=1; x=1; 1:X8=1; 1:X6=2; 1:X2=0; 1:X0=1;